When designing a system-on-chip or integrated circuit (IC), there are numerous design considerations that must be taken into account, including for example clock frequency and power supply to various parts of the chip or circuit.
Ideally, a synchronous system is employed in circuit design, whereby the same clock signal is distributed to the circuit components in a patterned configuration, commonly known as a clock tree, in order that all of the circuit components of the circuit can receive the same clock signal in a synchronous manner (where designed to do so). As all of the components are configured to use the same clock signal, communication problems between the circuit components can be reduced (i.e. signals between components do not arrive on unexpected clock cycles). Many factors must be taken into account when designing the clock tree, such as clock skew, whereby the clock signals on separate branches of the clock tree are designed to arrive at the same time at different corresponding points but actually arrive at different times, the difference being a skew between times of arrival. These considerations place a burden on the design manufacturing process and also make it difficult for a chip, having multiple functions and processes, to be designed in a cost-effective and timely manner.
The design layout of the chip and distribution of clock signals has been made even more difficult due to many chip designs having multiple “power domains”, whereby different areas of the chip are isolated and controlled with a switch that can cut off the voltage supply to that area of the chip. Multiple power domains can be used, for example, to address the problem of transistor leakage current in chips, whereby transistors leak current even when not active. This leakage current becomes even more of a problem as transistors get smaller and the number of transistors on a chip increase, and therefore the leakage current contributes significantly to the entire current consumption of the chip. The power domain switches can therefore be used to cut off the voltage supply to each power domain in order to suppress this current leakage. Some power domains are arranged so that they have different operating voltages thereby forming voltage domains. These can be used for further reduction in total power consumption. The voltage domains can have lower frequency components and lower voltages, which leads to a lower power consumption. However, a drawback to using voltage domains is that voltage level shifters are required in order to match the signal voltage levels at the boundaries between each voltage domain.
If designing a chip using a synchronous system, the design of these individual power domains would be heavily constrained due to having to conform to the design of the synchronous clock tree. It is therefore commonplace to design power domains so that they are asynchronous with respect to one another (i.e. they run at different clock speeds or frequencies, and/or the clock signals used in each power domain have different unknown phase offsets), therefore reducing the complexity of the clock tree design (as a full chip balanced (synchronous) clock tree is not required, which would be complex and would consume large amounts of power). This means that the overall design and manufacture process is quicker and more cost-effective.
In order for the different asynchronous domains (such as power domains or voltage domains, or indeed other regions or domains that simply run at different clock speeds or at least that are otherwise not synchronous with each other) to communicate with each other (i.e. so that data can be passed between the different domains). First-In-First-Out (FIFO) modules can be used to bridge between at least two of the asynchronous domains. FIFOs are modules, circuit components, circuit arrangements, software algorithms, data structures or logical arrangements, whether physical or otherwise, that enable data to be written to and read from a memory buffer. FIFOs are arranged so that the first data value written to the memory buffer will be the first data value that is read from the memory buffer, the second data value written to the memory buffer will be the second data value that is read from the memory buffer, etc.
In an asynchronous circuit design (i.e. a chip in which the different clock domains, sometimes due to the formation of power domains, are clocked at different speeds and/or have an unknown phase relationship with respect to each other), timing becomes an issue for a FIFO that bridges between the two asynchronous domains, because the write speed may differ from the read speed and therefore there is a risk of overflow or underflow and circuit malfunction. The asynchronous crossing creates an unwanted latency. Overflow is where data is lost due to the write speed being quicker than the read speed such that, when a memory buffer of the FIFO is filled, all of the excess data values that cannot be written to the already-full memory either overwrite other data values that have yet to be read or are lost. Underflow is where the write speed is slower than the read speed such that the capacity of the FIFO memory buffer is in excess such that the FIFO is not working at an optimum rate. The overflow and underflow situations therefore have deleterious effects on the chip requirements of throughput and latency.
Synchronisers are used to synchronise exchanged data between the different domains. The synchronisers enable the domains to communicate with each other more reliably but have a tendency to cause delays in the circuit whilst synchronising data. Therefore, for example, an indication signal representative of when the FIFO memory buffer is full sent from a FIFO memory buffer in a first domain to a FIFO write module in a second domain that is asynchronous with the first domain would be delayed as the indication signal is synchronised from one domain to the other. Due to this delay, an overflow of the FIFO memory buffer could occur until the indication signal is received.